The MKA Law and the
Milutinovic–Katulevskiy Architecture:
A Post-Moore Roadmap for AI-Scale,
Photonic, and Quantum-Adjacent Computing
Authors: Katulevskiy, Daniil
Katulevskaya, Elizaveta
Katulevskiy, Aleksey
and Milutinović, Veljko
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Abstract
Progress beyond conventional transistor scaling increasingly depends on whether gains
in devices, memory, interconnects, compilers, and
system software survive integration into complete
workloads. The Milutinovic–Katulevskiy Architecture ´
(MKA) develops a common research framework for
this problem. Building on Veljko Milutinovic’s Honey- ´
comb architecture and graph-mapping lineage, MKA
treats computation, stored state, communication,
placement, and physical substrate as one architectural design space. The article formulates a broader
system-level principle: a local hardware improvement counts as genuine architectural progress only
when its advantage survives data movement, state
placement, interfaces and conversion, scheduling
and queueing, accuracy, reliability, and servicelevel constraints at the boundary of completed
useful work. The proposed MKA Law operationalizes
this principle through the energy–time product of
completed workloads under fixed quality and service
requirements.
Communication bounds, placement models,
uncertainty-aware optimization, and substratespecific break-even conditions determine when locality, reuse, heterogeneous execution, and changes
of physical medium can improve the whole system.
An exact reference planner makes one part executable. Across a synthetic planning study, coordinated placement improves feasible plans relative
to local and fixed-placement strategies; strong
global alternatives recover most of that benefit.
Full accounting for movement and setup prevents
decisions that look attractive locally but fail system
constraints. These results establish a starting point
for calibrated hardware, concurrent graph workloads,
and experimental implementations.
MKA follows the quantitative architecture tradition
developed by John L. Hennessy and David A. Patterson, where workload, compiler, machine, memory,
communication, and implementation technology are
evaluated together. Oskar Mencer’s dataflow work
supplies an implementation precedent for compilerdirected spatial execution. Mor Harchol-Balter’s
queueing and server-power research connects execution capacity to delivered service. Dimitris Bertsimas’s robust and prescriptive optimization provides
the uncertainty-aware decision layer. Daniela Rus’s
graph grammars, decentralized control, and physical
co-design motivate search over realizable, controllable structures.
MKA organizes these ideas into six regimes
spanning reconfigurable digital fabrics, analog computation, processing near memory, photonic interconnects, quantum-dot systems,
and entanglement-assisted architectures for quantum-native workloads.
Artificial intelligence infrastructure provides an
immediate high-pressure application, while scientific
simulation, finance, genomics, telecommunications,
and other graph-intensive domains broaden the
research space.
At datacenter scale, sustained system-level efficiency improvements could translate into major
reductions in energy use and operating cost; in
science, the same gains could enlarge the computations achievable within finite power and time
budgets. MKA therefore proposes more than an
individual accelerator design: it establishes a shared
architectural language and an experimentally falsifiable research direction intended to carry useful
design knowledge across successive generations
of computing technology.
Prospectively, the MKA Law can be applied to
open-weight LLM serving as a six-vector optimization over compute and precision, resident weights,
KV and request state, expert and interconnect
routing, batching and queueing, and active capacity with its power and cooling burden. Llama 4
Maverick, GLM-5.3, Kimi K3, and Qwen3.8 expose
different resource demands, motivating modelspecific operating-point searches. At hyperscale,
the economic leverage is substantial: under a 5-GW
average AI-serving load, PUE 1.20, and electricity
at $0.07/kWh, every 10% reduction in system-level
IT energy per completed request corresponds to
approximately $368 million in annual electricity
savings at fixed demand and unchanged PUE. A 30%
reduction would exceed $1.1 billion annually. These
figures are sensitivity thresholds, not assumed
MKA performance, and illustrate the scale at which
experimentally measured system-level gains would
translate into economic impact.
Keywords
Computer architecture, dataflow,
energy–delay product, graph placement, heterogeneous computing,
large language models, queueing, robust optimization.
Published in: IPSI Transaction on Internet Research
(Volume: 22, Issue: 4)
Publisher: IPSI, Belgrade
Date of Publication: October 1, 2026
Open Access: CC-BY-NC-ND
DOI: https://doi.org/10.58245/ipsi.tir.2604.04
Pages: 16 - 41
ISSN: 1820 - 4503
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Katulevskiy, Daniil
Daniil Katulevskiy is a computer scientist and systems
researcher working on artificial intelligence infrastructure,
heterogeneous computing, distributed
inference, accelerator performance, edge computing, and post-Moore computer architecture. He
graduated in Computer Science from the University of California, San Diego. His technical
work includes AI and performance engineering on
Qualcomm and NVIDIA computing platforms, with
particular emphasis on memory movement, accelerator utilization, model serving, and system-level
efficiency. Daniil is the lead author and primary
technical contributor to the present formulation
of the Milutinovic–Katulevskiy Architecture (MKA). ´
His contributions include the completed-work measurement framework
and MKA progress criterion, the workload and admissibility model, graph
placement and communication analysis, the exact reference-planning formulation,
heterogeneoussubstrate break-even models, large-model serving
analysis, uncertainty-aware validation, and the connection between system-level efficiency
and datacenter economics. His broader research interests
include scalable AI systems, secure and privacypreserving computing, and new computational
architectures that combine hardware, software,
communication, and physical constraints within a
common systems framework.
E-mail: dkatulevskiy@gmail.com, ORCID: 0009-0002-7732-3628