Journal: IPSI Transactions on Internet Research


Editorial:
From Silicon to Society:
Efficiency, Security, and Responsible
Integration of Artificial Intelligence

Author: Ivan Ratković


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Abstract


The progress of artificial intelligence (AI) is no longer determined by algorithms and models alone. It depends equally on the hardware on which AI workloads are executed, on the security of models once they are deployed, and on the ability of organizations to integrate AI responsibly into everyday practice. This special issue brings together contributions that address these challenges at different levels - from post-Moore computing substrates and the confidentiality of trained neural networks to AI-supported clinical workflows, the use of generative AI in higher education, and the data-driven operation of electric power grids on the path to decarbonization.

Although the papers belong to distinct research fields, they share a common perspective: rather than evaluating an isolated component, they examine how technology behaves as part of a larger system. They show how total energy and data movement determine the efficiency of AI hardware, how the outputs of a deployed model can reveal the model itself, how physics-based models and machine learning can be combined to manage uncertainty in the power grid, and how data, analytics, institutional policies, and human judgment must be coordinated for AI to deliver real value in hospitals and universities. By combining formal, experimental, and empirical approaches, the issue aims to stimulate dialogue between the hardware, security, and application communities.

Even though the papers in this issue address different domains and levels of abstraction, they converge on a common conclusion: the impact of AI and other computational methods is determined not only by the capabilities of models and algorithms, but also by the efficiency with which they are executed, the protection of the knowledge they embody, their grounding in the physics of the infrastructure they help to operate, and the workflows, policies, and competencies that govern their use. We hope that readers will find these contributions useful and that they will inspire further research across disciplinary boundaries. We sincerely thank all the authors for their contributions and the reviewers for their careful and constructive evaluations.




Published in: IPSI Transaction on Internet Research (Volume: 22, Issue: 4)

Publisher: IPSI, Belgrade

Date of Publication: October 1, 2026

Open Access: CC-BY-NC-ND

Pages: 1 - 4

ISSN: 1820 - 4503



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Ivan Ratković

Ivan Ratković, PhD, is a computer architect with twenty years of experience in designing, architecting, developing, and taping out energy-efficient multicore processors and hardware accelerators for artificial intelligence (AI) and high-performance computing (HPC). He is a Chief Architect and CTO of a company developing area- and power-efficient HPC/AI processors, where he leads architecture, design, and verification, with a special focus on the dot-product unit, the RISC-V IOMMU, and the RISC-V vector processing unit. Previously, at Esperanto Technologies, he served as Power Manager and Architect, leading all power- and energy-efficiency efforts - from applications and the operating system down to silicon - for a RISC-V system-on-chip for HPC and AI. Earlier, as a member of the company’s senior VLSI technical staff, he worked on vector/tensor unit design, power estimation and optimization, low-power and full-chip verification, gate-level sign-off, and silicon validation, contributing to the successful tape-out of a 24-billion-transistor chip with more than a thousand RISC-V vector cores.

Dr. Ratković received his PhD in Computer Architecture, cum laude, from the Universitat Politècnica de Catalunya (UPC-BarcelonaTech), within a doctoral program run jointly with the Barcelona Supercomputing Center (BSC) and completed partly at UC Berkeley (International Doctorate). His thesis addressed the design of power- and energy-efficient functional units for vector processors. He has published in venues such as IEEE Transactions on VLSI Systems, ACM Transactions on Architecture and Code Optimization, ISLPED, and the Journal of Big Data, serves as a reviewer for IEEE Transactions on VLSI Systems, and has served on a PhD defense committee at UPC-BarcelonaTech. His interests include computer architecture, vector processors, floating-point arithmetic, low-power and energy-efficient design, VLSI, RISC-V, and machine learning.
Email: ivan.bcn.bgd@gmail.com, ORCID ID: 0000-0002-0524-7227.